1. Field of the Invention
This invention relates generally to metal-insulator-metal (MIM) capacitors, and more particularly to a method for forming an enhanced MIM capacitor having a three dimensional structure with an increased and more tightly controlled capacitance and reduced parasitics without occupying additional area over existing three dimensional MIM capacitor designs.
2. Description of the Background
In high frequency applications, the elimination of parasitic resistance in capacitor electrodes is a critical factor in controlling the frequency dependence of the capacitor. Metal-insulator-metal (MIM) capacitors have low electrode resistances, and have been implemented in integrated circuits requiring high-speed performance. In addition, MIM capacitors have capacitance values that have a low correlation to voltage and temperature variation, thereby providing consistent performance over a wide operating range. A traditional approach to constructing a MIM capacitor utilizes two horizontal parallel conductive plates (electrodes) separated by a dielectric. However, the horizontal plate MIM capacitor required a relatively large surface area to implement a given capacitance value, and in a high-density integrated circuit environment surface area (real estate) is at a premium. The relatively large surface area of the horizontal plate MIM capacitor also leads to additional coupling noise between the MIM capacitor and surrounding dielectric substrate, which is not desirable in RF (radio frequency) applications.
In an effort to achieve higher specific capacitance values (capacitance per unit area) three dimensional capacitors have been constructed. The three dimensional capacitors add a vertical dimension to the two dimensional horizontal plate capacitor construction. The three dimensional capacitor construction provides for areas of additional overlap of the conductive plates in a given footprint, thereby increasing the overall specific capacitance. Existing three dimensional MIM capacitor constructs include interlocking digits or fingers separated by a dielectric, where the interlocking fingers form the electrodes. A second variation has pillars that extend from the face of one electrode, and are surrounded by the second electrode, with a dielectric disposed between the two electrode formations. Examples of these three dimensional MIM capacitors are presented in U.S. Pat. No. 6,825,080 (Yang et al.).
However, the three dimensional MIM capacitors presented by Yang et al. employ a partial subtractive etch processes to form the trenches that serve as a receptacle for the second electrode. Yang et al. rely on a timed subtractive etch with no etch stop, which can lead to a variance in trench depth, and an ensuing capacitance variability. In addition, the subtractive etch of Yang et al. is designed to only extend between 24 and 80 percent of the thickness of the conductive layer forming the bottom electrode of the MIM capacitor, thereby limiting the potential amount of overlap between the top and bottom electrodes and the resultant specific capacitance. Finally, the MIM capacitors proposed by Yang et al. are formed above the wiring layer metal, and require vias to connect to the top electrode, potentially introducing additional parasitic affects (i.e. lead inductance) to the circuit.